Features: ` 4000-V(peak) Isolation UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2) IEC 61010-1 and CSA Approved 50 kV/s Transient Immunity Typical` Signaling Rate 0 Mbps to 150 Mbps Low-Propagation Delay Low Pulse-Width Distortion` High-Electromagnetic Immunity` Low-Input Current Requirement` Failsafe O...
ISO721: Features: ` 4000-V(peak) Isolation UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2) IEC 61010-1 and CSA Approved 50 kV/s Transient Immunity Typical` Signaling Rate 0 Mbps to 150 Mbps Low-Propagation Delay ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
VCC | Supply voltage,VCC1,VCC2 |
0.5 V to 6 V | |||
VI | Voltage at IN or OUT terminal |
0.5 V to 6 V | |||
IO | Output Current |
±15 mA | |||
ESD | Electrostatic discharge | Human Body Model | JEDEC Standard 22, Test Method A114-C.01 | All pins |
±2 kV |
Charged Device Model | JEDEC Standard 22, Test Method C101 |
±1 kV | |||
TJ | Maximum junction temperature |
170°C |
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This isolator is suitable for basic insulation applications within the safety limiting data. Maintenance of the safety data must be ensured by means of protective circuitry.
The ISO721 and ISO721M digital isolators have a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 s, the input is assumed to be unpowered or not functional, and the failsafe circuit drives the output to a logic high state.