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IS45S16400C1

Features: • Clock frequency: 143 MHz• Fully synchronous; all signals referenced to a positive clock edge• Internal bank for hiding row access/precharge• Single 3.3V power supply• LVTTL interface• Programmable burst length (1, 2, 4, 8, full page)• Programma...

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SeekIC No. : 004379074 Detail

IS45S16400C1: Features: • Clock frequency: 143 MHz• Fully synchronous; all signals referenced to a positive clock edge• Internal bank for hiding row access/precharge• Single 3.3V power sup...

IS45S16400C1 Data Sheet

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Part Number:
IS45S16400C1
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Clock frequency: 143 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Byte controlled by LDQM and UDQM
• Automotive Temperature Range Option A: 0oC to +70oC Option A1: -40oC to +85oC
• Package: 400-mil 54-pin TSOP II
• Lead-free package is available


Pinout

Connection Diagram


Specifications

Symbol
Parameters
Rating
Unit
V DD MAX
V DDQ
M AX
VIN
VOUT
P D MAX
ICS
TOPR
TSTG
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Allowable Power Dissipation
Output Shorted Current
Operating Temperature A A1
Storage Temperature
1.0 to +4.6
1.0 to +4.6
1.0 to +4.6
1.0 to +4.6
1
50
0 to +70
-40 to +85
55 to +150
V
V
V
V
W
mA
°C
°C
°C

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.




Description

ISSI's 64Mb Synchronous DRAM IS45S16400C1 is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.




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