IS42VS16400C1

Features: • Clock frequency: 100, 83, 66 MHz• Fully synchronous; all signals referenced to a positive clock edge• Internal bank for hiding row access/precharge• Single 1.8V power supply• LVTTL interface• Programmable burst length (1, 2, 4, 8, full page)• P...

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IS42VS16400C1 Picture
SeekIC No. : 004379060 Detail

IS42VS16400C1: Features: • Clock frequency: 100, 83, 66 MHz• Fully synchronous; all signals referenced to a positive clock edge• Internal bank for hiding row access/precharge• Single 1.8V p...

floor Price/Ceiling Price

Part Number:
IS42VS16400C1
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• Clock frequency: 100, 83, 66 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 1.8V power supply
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Byte controlled by LDQM and UDQM
• Industrial temperature availability
• Package: 400-mil 54-pin TSOP II
• Lead-free package is available



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VDD MAX

VDDQ MAX

VIN
Maximum Supply Voltage

Maximum Supply Voltage for Output Buffer

Input Voltage
0.5 to +2.6

0.5 to +2.6

0.5 to +2.6
V

V

V
PD MAX

ICS
Allowable Power Dissipation

Output Shorted Current
1

50
W

mA
TOPR Operating Temperature Com
Ind.
0 to +70
-40 to +85

TSTG Storage Temperature 55 to +150




Description

ISSI's 64Mb Synchronous DRAM IS42VS16400C1 is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.




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