IS42VS16100C1

Features: • Clock frequency: 100 MHz• Fully synchronous; all signals referenced to apositive clock edge• Two banks can be operated simultaneously andindependently• Dual internal bank controlled by A11(bank select)• Single 1.8V power supply• LVTTL interface•...

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IS42VS16100C1 Picture
SeekIC No. : 004379059 Detail

IS42VS16100C1: Features: • Clock frequency: 100 MHz• Fully synchronous; all signals referenced to apositive clock edge• Two banks can be operated simultaneously andindependently• Dual inter...

floor Price/Ceiling Price

Part Number:
IS42VS16100C1
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• Clock frequency: 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single 1.8V power supply
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Package 400-mil 50-pin TSOP II
• Lead-free package option



Pinout

  Connection Diagram


Specifications

Symbol Parameters Rating Unit
VCC MAX Maximum Supply Voltage 0.5 to +2.6 V
VCCQ MAX Maximum Supply Voltage for Output Buffer 0.5 to +2.6 V
VIN Input Voltage 0.5 to +2.6 V
PD MAX Allowable Power Dissipation 1 W
ICS Output Shorted Current 50 mA
TOPR Operating Temperature Com
Ind.
0 to +70
-40 to +85

TSTG Storage Temperature 55 to +150



Description

ISSI's 16Mb Synchronous DRAM IS42VS16100C1 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.




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