IS42S32200

Features:

* Clock frequency: 166, 143 MHz
* Fully synchronous; all signals referenced to a positive clock edge
* Internal bank for hiding row access/precharge
* Single 3.3V power supply
* LVTTL interface
* Programmable burst length
  (1, 2, 4, 8, full page)
* Programmable burst sequence:
   Sequential/Interleave
* Self refresh modes
* 4096 refresh cycles every 64 ms
* Random column address every clock cycle
* Programmable CAS latency (2, 3 clocks)
* Burst read/write and burst read/single write operations capability
* Burst termination by burst stop and precharge command
* Industrial temperature availability
* Package 400-mil 86-pin TSOP II


Pinout




Description

The 64Mb SDRAM IS42S32200 is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits.  Internally configured as a quad-bank DRAM with a synchronous interface.  Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits.

The 64Mb SDRAM IS42S32200 includes an AUTO REFRESH MODE and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK All inputs and outputs are LVTTL compatible.

The 64Mb SDRAM IS42S32200 has the ability to synchronously burs data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly
change column addresses on each clock cycle during burst access.