IS42S16400A

Features:

* Clock frequency:166, 133, 100 MHz
* Fully synchronous; all signals referenced to a positive clock edge
* Internal bank for hiding row access/precharge
* Single 3.3V power supply
* LVTTL interface
* Programmable burst length
   (1, 2, 4, 8, full page)
* Programmable burst sequence:
   Sequential/Interleave
* Self refresh modes
* 4096 refresh cycles every 64 ms
* Random column address every clock cycle
* Programmable CAS latency (2, 3 clocks)
* Burst read/write and burst read/single write operations capability
* Burst termination by burst stop and precharg command
* Byte controlled by LDQM and UDQM
* Industrial temperature availability (133MHz, 100MHz)
* Package:  400-mil 54-pin TSOP II, a lead-free package is available.


Pinout




Specifications

Symbol             Parameters                                                       Rating                      Unit
V_CC                  MAX Maximum Supply Voltage                          1.0 to +4.6             V
V_{CCQ  MAX}        Maximum Supply Voltage for Output Buffer      1.0 to +4.6             V 
V_IN                   Input Voltage                                                   1.0 to +4.6             V
V_OUT                Output Voltage                                                 1.0 to +4.6             V
P_{D MAX}             Allowable Power Dissipation                                      1                      W
I_CS                   Output Shorted Current                                            50                   mA
T_OPR                Operating Temperature     Com.                           0 to +70              °C
                                                                  Ind.                           40 to +85
T_STG                Storage Temperature                                          55 to +150         °C


Description

The 64Mb SDRAM IS42S16400A is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits.  Internally configured as a quad-bank DRAM with a synchronous interface.  Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.

The 64Mb SDRAM IS42S16400A includes an AUTO REFRESH MODE,and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.

The 64Mb SDRAM IS42S16400A has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.