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IS42S16100C1

Features: • Clock frequency: 200, 166, 143 MHz• Fully synchronous; all signals referenced to a positive clock edge• Two banks can be operated simultaneously and independently• Dual internal bank controlled by A11 (bank select)• Single 3.3V power supply• 2.5V VDD...

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SeekIC No. : 004379032 Detail

IS42S16100C1: Features: • Clock frequency: 200, 166, 143 MHz• Fully synchronous; all signals referenced to a positive clock edge• Two banks can be operated simultaneously and independently•...

IS42S16100C1 Data Sheet

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Part Number:
IS42S16100C1
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Two banks can be operated simultaneously and independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• 2.5V VDD option available
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Byte controlled by LDQM and UDQM
• Industrial temperature up to 143 MHz
• Package 400-mil 50-pin TSOP II
• Lead-free package option


Pinout

Connection Diagram


Specifications

Symbol
Parameters
Rating
Unit
V DD MAX
 Maximum Supply Voltage
1.0 to +4.6
V
V DDQ MAX
 Maximum Supply Voltage for Output Buffer
1.0 to +4.6
V
VIN
 Input Voltage
1.0 to +4.6
V
VOUT
 Output Voltage
1.0 to +4.6
V
P D MAX
 Allowable Power Dissipation
1
W
ICS
 Output Shorted Current
50
mA
TOPR
 Operating Temperature
Com
Ind.
0 to +70
-40 to +85
°C
°C
TSTG
 Storage Temperature
55 to +150
°C



Description

ISSI's 16Mb Synchronous DRAM IS42S16100C1 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.


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