ICS8432I-101

Features: • Dual differential 3.3V LVPECL outputs• Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK• TEST_CLK can accept the following input levels: LVCMOS or LVTTL• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL• CLK,...

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ICS8432I-101 Picture
SeekIC No. : 004371028 Detail

ICS8432I-101: Features: • Dual differential 3.3V LVPECL outputs• Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK• TEST_CLK can accept the following input levels: LVCMOS or LVTTL• CLK, nCLK p...

floor Price/Ceiling Price

Part Number:
ICS8432I-101
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/6/6

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Product Details

Description



Features:

• Dual differential 3.3V LVPECL outputs
• Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK
• TEST_CLK can accept the following input levels: LVCMOS or LVTTL
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK, nCLK or TEST_CLK maximum input frequency: 40MHz
• Output frequency range: 25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Accepts any single-ended input signal on CLK input with resistor bias on nCLK input
• Parallel interface for programming counter and output dividers
• RMS period jitter: 5ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant



Pinout

  Connection Diagram


Specifications

Supply Voltage, VCC ..............4.6V
Inputs, VI............   -0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current...............  50mA
Surge Current ................100mA
Package Thermal Impedance, JA.. 47.9/W (0 lfpm)
Storage Temperature, TSTG......   -65 to 150



Description

The ICS8432I-101 is a general purpose, dual output Differential-to-3.3V LVPECL high frequency synthesizer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8432I-101 has a selectable TEST_CLK or CLK, nCLK inputs. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input differential or single ended reference frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the ICS8432I-101 makes it an ideal clock source for Gigabit Ethernet and SONET applications.




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