Features: • Accepts various HD and SD references including hsync,transport and pixel clock rates• Outputs HD and SD pixel rates• One LVCMOS/LVTTL PLL clock output• Two selectable LVCMOS/LVTTL input clocks• LVCMOS input select lines• VCXO PLL bandwidth can be opt...
ICS810001-21: Features: • Accepts various HD and SD references including hsync,transport and pixel clock rates• Outputs HD and SD pixel rates• One LVCMOS/LVTTL PLL clock output• Two select...
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Supply Voltage, VDD........................................ 4.6V
Inputs, VI................................ -0.5V to VDD + 0.5V
Outputs, VO.......................... -0.5V to VDDO + 0.5V
Package Thermal Impedance, JA.... 34.8/W (0 lfpm)
Storage Temperature, TSTG........... -65 to 150
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
The ICS810001-21 is a member of the HiperClockS™ family of high performance clock solutions from ICS. The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series.
The first stage of the ICS810001-21 is a VCXO PLL that is optimized to provide reference clock jitter attenuation, and to support the complex
PLL multiplication ratios needed for video rate conversion.The second stage is a FemtoClock frequency multiplier that provides the low jitter, high frequency video output clock.
Preset multiplication ratios of the ICS810001-21 are selected from internal lookup tables using device input selection pins. The multiplication ratios are optimized to support most common video rates used in professional video system applications. The VCXO requires the use of an external, inexpensive pullable crystal. Two crystal connections are provided (pin selectable) so that both 60 and 59.94 base frame rates can be supported. The VCXO requires external passive loop filter components which are used to set the PLL loop bandwidth and damping characteristics.