Features: • (2) Differential LVPECL outputs
• Selectable CLKx, nCLKx differential input pairs
• CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels
• Maximum output frequency: 700MHz
• FemtoClock VCO frequency range: 560MHz - 700MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 0.81ps (typical)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• -40°C to 85°C ambient operating temperaturePinout
SpecificationsSupply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6V
Inputs, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC + 0.5V
Outputs, VO (LVCMOS) . . . . . . . . . . . . . . . . -0.5V to VCCO + 0.5V
Outputs, IO (LVPECL)
Continuous Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mA
Surge Current 100mA
Package Thermal Impedance, JA . . . . . . . . . .34.8°C/W (0 lfpm)
Storage Temperature, TSTG . . . . . . . . . . . . . . . .-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DescriptionThe ICS843002I-41 is a member of the HiperClockS™ family of high performance clock solutions from ICS. The ICS843002I-41 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The ICS843002I-41 contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock™ VCO. PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non-FEC (non-Forward Error Correction) SONET/SDH applications with rates up to OC-48 (SONET) or STM-16 (SDH). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application.
The ICS843002I-41 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. "Hitless switching" is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks.
Typical ICS843002I-41 configuration in SONET/SDH Systems:
• VCXO 19.44MHz crystal
• Loop bandwidth: 50Hz - 250Hz
• Input Reference clock frequency selections: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz
• Output clock frequency selections: 19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz, Hi-Z
ICS843002I-41 Data Sheet
