Features: • Twelve LVCMOS/LVTTL outputs• Selectable LVCMOS/LVTTL clock or differential CLK, nCLK inputs• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL• LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL•...
ICS83948I-147: Features: • Twelve LVCMOS/LVTTL outputs• Selectable LVCMOS/LVTTL clock or differential CLK, nCLK inputs• CLK, nCLK pair can accept the following differential input levels: LVPECL, ...
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Features: • Accepts various HD and SD references including hsync,transport and pixel clock r...
Supply Voltage, VDD 4.6V
Inputs, VI -0.5V to VDD + 0.5 V
Outputs, VO -0.5V to VDDO + 0.5V
Package Thermal Impedance, JA 47.9/W (0 lfpm)
Storage Temperature, TSTG -65 to 150
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
The ICS83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS83948I-147 has two selectable clock inputs.
The CLK, nCLK pair of the ICS83948I-147 can accept most standard differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines.
The ICS83948I-147 is characterized at full 3.3V or full 2.5V operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83948I-147 ideal for those clock distribution applications demanding well defined performance and repeatability.