ICS83840B

Supply Voltage, V_DD .............-0.5V to +3.3V
Inputs, V_I -0.3V to V_DD ...............+ 0.3 V
Ports
DC Input Clamp Current, I_IK............. -50mA
Package Thermal Impedance, _JA....50.04/W (0 mfps)
Storage Temperature, T_STG......... -65 to 150

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

The ICS83840B is a DDR SDRAM MUX and is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS83840B has 10 Host Lines and each host line can be passed to 4 Data Ports. The 10 channels are allocated as follows in the DDR SDRAM application: 8 data lines, 1 strobe line and 1 DQm line. The Host/ Data Ports are compatible with single-ended SSTL-2 and the device operates from a 2.5V supply.

Guaranteed low output skew makes the ICS83840B ideal for demanding applications which require well defined performance and repeatability.