Features: • 4 LVCMOS/LVTTL outputs• Selectable differential or LVCMOS/LVTTL clock inputs• CLK, nCLK pair can accept the following differentialinput levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL• LVCMOS_CLK supports the following input types:LVCMOS, LVTTL• Maximum output fr...
ICS8305: Features: • 4 LVCMOS/LVTTL outputs• Selectable differential or LVCMOS/LVTTL clock inputs• CLK, nCLK pair can accept the following differentialinput levels: LVPECL, LVDS, LVHSTL, HC...
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Features: • Accepts various HD and SD references including hsync,transport and pixel clock r...
The ICS8305 is a low skew, 1-to-4, Differential/LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable isinternally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A sepa-rate output enable pin controls whether the outputs are in the active or high impedance state.Guaranteed output and part-to-part skew characteristics makethe ICS8305 ideal for those applications demanding well de-fined performance and repeatability.