Features: `One 3.3V or 2.5V LVPECL output pair`Two selectable crystal oscillator interfaces for the VCXO,one differential clock or one LVCMOS/LVTTL clock inputs`CLK1/nCLK1 supports the following input types:LVPECL, LVDS, LVHSTL, SSTL, HCSL`Crystal operating frequency range: 14MHz - 24MHz`VCO range...
ICS813001I: Features: `One 3.3V or 2.5V LVPECL output pair`Two selectable crystal oscillator interfaces for the VCXO,one differential clock or one LVCMOS/LVTTL clock inputs`CLK1/nCLK1 supports the following inp...
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Features: • Accepts various HD and SD references including hsync,transport and pixel clock r...
Supply Voltage, VCC .............. 4.6V
Inputs, VI ............-0.5V to VCC + 0.5V
Outputs, IO (LVPECL) Continuous Current ...50mA
Surge Current ................100mA
Package Thermal Impedance, JA..70/W (0 lfpm)
Storage Temperature, TSTG......-65 to 150
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
The ICS813001I is a dual VCXO + FemtoClockTM Multiplier designed for use in Discrete PLL loops. Two selectable external VCXO crystals allow the device to be used in multi-rate applications, where a given line card can be switched, for example, between 1Gb Ethernet (125MHz system reference clock) and 1Gb Fibre Channel (106.25MHz system reference clock) modes. Of course,a multitude of other applications are also possible such as switching between 74.25MHz and 74.175824MHz for HDTV, switching between SONET, FEC and non FEC rates, etc.
The ICS813001I is a two stage device - a VCXO followe by a FemtoClock PLL. The FemtoClock PLL can multiply the crystal frequency of the VCXO to provide an output frequency range of 40.83MHz to 640MHz, with a random rms phase jitter of less than 1ps (12kHz-20MHz). This phase jitter performance meets the requirements of 1Gb/10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel,and SONET up to OC48. The FemtoClock PLL can also be bypassed if frequency multiplication of the ICS813001I is not required. For testing/debug purposes, de-assertion of the output enable pin will place both Q and nQ in a high impedance state.