Features: SpecificationsDescriptionThe ICD2062B has the following features including Second generation dual oscillator graphics clock generator;PECL Video Outputs: 508 kHz to 165 MHz;TTL Outputs: 508 kHz to 120 MHz;Individually programmable PLLs using a highly reliable, Manchester-encoded, 21-bit ...
ICD2062B: Features: SpecificationsDescriptionThe ICD2062B has the following features including Second generation dual oscillator graphics clock generator;PECL Video Outputs: 508 kHz to 165 MHz;TTL Outputs: 50...
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The ICD2062B has the following features including Second generation dual oscillator graphics clock generator;PECL Video Outputs: 508 kHz to 165 MHz;TTL Outputs: 508 kHz to 120 MHz;Individually programmable PLLs using a highly reliable, Manchester-encoded, 21-bit serial data word;2-pin serial programming interface allows direct connection to most graphics chip sets with no external hardware required;Programmable video clock dividers allow for easy interface to most RAMDACs and VRAMs;Three-state oscillator control disables outputs for test purposes.
The ICD2062B is a clock generator for high-resolution video displays. It uses a low-frequency, low-cost reference crystal to produce the following: a 10 K compatible complementary ECL output signal for high-speed video RAMDACs, a high-speed TTL output signal for video RAMS and system logic operation,and the requisite load, control, and clock signals to control the loading of data between the CRT controller, VRAM, and RAM-DACs.The ICD2062B Dual Programmable Clock Generator offers two fully user-programmable phase-locked loops in a single package. The outputs may be changed "on the fly"to any desired frequency value in the range 508 kHz to 165 MHz (VCLK-OUT)and 508 kHz to 120 MHz (MCLKOUT). The ICD2062B is ideally suited for any design where multiple or varying frequencies are required, replacing more expensive metal can oscillators, particularly where the application requires expensive complementary ECL oscillators.
The Video Clock output may be programmatically divided-by 1, 2, 3, 4, 5, or 8-in order to generate the Load Signal, which is further divided by 2 and 4 for clocking video timing logic. A second Load Signal may be synchronously gated in order to enable starting and stopping the clocking of video RAMs. The ICD2062B can also configure the pipeline delay of certain RAMDACs (such as the Bt457/458) to a fixed pipeline delay.Some examples of the uses for this device include: graphics board dot clocks to allow dynamic synchronization with different brands of monitors or display formats; and on-board test strategies where the ability to skew a system's desired frequency allows worst case evaluations.