Features: • High-speed access times: 55, 70, 100 ns• CMOS low power operation ICC=18mA (typical)* operating ISB2=3µA (typical)* CMOS standby• TTL compatible interface levels• Single 2.7V-3.6V Vcc power supply• Fully static operation: no clock or refresh required...
IC62LV51216L: Features: • High-speed access times: 55, 70, 100 ns• CMOS low power operation ICC=18mA (typical)* operating ISB2=3µA (typical)* CMOS standby• TTL compatible interface levels&...
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Features: • Access times of 45, 55, and 70 ns• Low active power: 60 mW (typical)•...
Features: • Access times of 45, 55, and 70 ns• Low active power: 60 mW (typical)•...
Features: SpecificationsDescriptionThe IC62LV12816L are high-speed,2.097,152-bit static RAMs organ...
Symbol | Parameter | Value | Unit |
VTERM TBIAS VCC TSTG PT |
Terminal Voltage with Respect to GND Temperature Under Bias Vcc related to GND Storage Temperature Power Dissipation |
0.5 to Vcc + 0.5 40 to +85 0.3 to +4.0 65 to +150 1.0 |
V V W |
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The IC62LV51216L are low-power, 8.388,608 bit static RAMs organized as 524,288 words by 16 bits. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.
When CE1 of the IC62LV51216L is HIGH or when CE2 is low (deselected) or both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE1, CE2 and OE.
The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC62LV51216L are packaged in the JEDEC standare 44-pin TSOP-2 and 48-pin 8*10mm TF-BGA.