IC61S25632T

Features: • Pipeline Mode operation• Single/Dual Cycl Deselect• User-selectable Output Drive Strength with XQ Mode• Internal self-timed write cycle• Individual Byte Write Control and Global Write• Clock controlled, registered address, data and control• Pen...

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SeekIC No. : 004370407 Detail

IC61S25632T: Features: • Pipeline Mode operation• Single/Dual Cycl Deselect• User-selectable Output Drive Strength with XQ Mode• Internal self-timed write cycle• Individual Byte Wri...

floor Price/Ceiling Price

Part Number:
IC61S25632T
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

• Pipeline Mode operation
• Single/Dual Cycl Deselect
• User-selectable Output Drive Strength with XQ Mode
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear burst sequence control using ODE input
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and 119-pin PBGA package
• Single +3.3V, +10%, 5% core power supply
• Power-down snooze mode
• 2.5V or 3.3V I/O Supply
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)



Application

The ICSI SyncBurst Pipelined SRAM family employs igh-speed ,low-power CMOS designs that are fabricated sing an advanced CMOS process to provide Level 2 ache applications supporting Pentium and PowerPC icroprocessors originally, the device now finds application anging from DSP main store to networking chip set upport.




Pinout

  Connection Diagram


Description

ICSI's 8Mb SyncBurst Pipelined SRAMs of the IC61S25632T integrate a 512k  18, 256k x 32, or 256k x 36 SRAM core with advanced ynchronous peripheral circuitry and a 2-bit burst counter.




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