HYS72T643x0HP3.7A

• 240-pin PC2-5300, PC2-4200 and PC23200 DDR2 SDRAM memory modules for PC, Workstation and Server main memory applications
• One rank 64M * 72, 128M * 72 and two ranks 128M * 72 module organization and 64M * 8, 128M * 4 chip organization
• 512 MByte and 1GByte module built with 512-Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply
• All speed grades faster than DDR2-400 comply with DDR2-400 timing specifications as well.
• VLP (Very Low Profile) Registered DIMM Parity bit for address and control bus
• Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type
• Auto Refresh (CBR) and Self Refresh.
• High Temperature Self Refresh is supported.
• Average Refresh Period 7.8 s at a TCASE lower than 85
°C, 3.9 s between 85 °C and 95 °C.
• All inputs and outputs SSTL_18 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT)
• Serial Presence Detect with E²PROM
• Based on standard reference layouts Raw Card "R", "T"and "U"
• RDIMM with parity Dimensions (nominal): 18.30 mm high,133.35 mm wide
• RoHS compliant products¹⁾

1) When V_DD and V_DDQ and V_DDL are less than 500 mV; V_REF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
  Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The HYS72T643x0HP3.7A module family are Very Low Profile (VLP) Registered DIMM (RDIMM with parity) with 18.30 mm height based on DDR2 technology. DIMMs are available as ECC modules in 64M x 72 (512 MByte) and 128M x 72 (1 GByte) organization and density, intended for mounting into 240-Pin connector sockets.

The memory array of the HYS72T643x0HP3.7A is designed with 512-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature of the HYS72T643x0HP3.7A serial presence detect based on a serial E²PROM device using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.