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HYS72D128020GR-7-B

Features: • 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main memory applications• One bank 32M × 72, 64M x 72, and two bank 64M x 72 and 128M × 72 organization• JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) with a single + 2.5 V (...

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SeekIC No. : 004369489 Detail

HYS72D128020GR-7-B: Features: • 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main memory applications• One bank 32M × 72, 64M x 72, and two bank 64M x 72 and 128M × 72 organiz...

HYS72D128020GR-7-B Data Sheet

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Part Number:
HYS72D128020GR-7-B
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main memory applications
• One bank 32M × 72, 64M x 72, and two bank 64M x 72 and 128M × 72 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) with a single + 2.5 V (± 0.2 V) power supply
• Built with 256Mbit DDR-I SDRAMs in 66- Lead TSOPII package
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Re-drive for all input signals using register and PLL devices.
• Serial Presence Detect with E2PROM
• Jedec standard MO-206 form factor: 133.35 mm(nom.) × 43.18 mm(nom.) × 4.00 mm (max.) (6,80 mm max. with stacked components)
• Jedec standard reference layout: Raw Cards A, B and C
• Gold plated contacts


Pinout

Connection Diagram


Specifications

Parameter Symbol Limit Values Unit
min. max.
Input / Output voltage relative to VSS VIN, VOUT 0.5 3.6 V
Input / Output voltage relative to VSS VDD, VDDQ 0.5 3.6 V
Storage temperature range TSTG -55 +150
Power dissipation (per SDRAM component) PD 1 W
Data out current (short circuit) IOS 50 mA



Description

The HYS72D128020GR-7-B are industry standard 184-pin 8-byte Dual in-lineMemory Modules (DIMMs) organized as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board.

The DIMMs feature of the HYS72D128020GR-7-B serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.




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