HYS72T6400HFD-3S-B

• 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications.
• Module organisation one rank 64M × 72,one rank 128M × 72, two ranks 128M × 72,two ranks 256M ×72
• JEDEC Standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V (± 0.1 V) power supply.
• Built with 512Mb DDR2 SDRAMs in 60-ball FBGA Chipsize Packages.
• Re-drive and re-sync of all address, command, clock and data signals using AMB (Advanced Memory Buffer).
• High-Speed Differential Point-to-Point Link Interface at 1.5 V (Jedec standard pending).
• Host Interface and AMB component industry standard compliant.
• Supports SMBus protocol interface for access to the AMB configuration registers.
• Detects errors on the channel and reports them to the host memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Automatic Channel Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• Hot Add-on and Hot Remove Capability.
• MBIST and IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Low profile: 133.35mm x 30.35 mm
• 240 Pin gold plated card connector with 1.00 mm contact centers (JEDEC standard pending).
• Based on JEDEC standard reference card designs (Jedec standard pending).
• SPD (Serial Presence Detect) with 256 Byte serial E²PROM.Performance:
• RoHS Compliant Products1)

1) When V_DD and V_DDQ and V_DDL are less than 500 mV; V_REF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

This document describes the electrical and mechanical features of a 240-pin, PC2-5300F ECC type, Fully Buffered Double-Data-Rate Two Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered DIMMs of the HYS72T6400HFD-3S-B use commodity DRAMs isolated from the memory channel behind a buffer on the DIMM. They are intended for use as main memory when installed in systems such as servers and workstations. PC2-5300 refers to the DIMM naming convention indicating the DDR2 SDRAMs running at 333 MHz clock speed and offering 5300 MB/s peak bandwidth. FB-DIMM features a novel architecture including the Advanced Memory Buffer. This single chip component of the HYS72T6400HFD-3S-B,located in the center of each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the DDR2 SDRAMs including data in- and output. The AMB communicates with the host controller and / or the adjacent DIMMs on a system board using an Industry Standard High-Speed Differential Point-to-Point Link Interface at 1.5 V.

The Advanced Memory Buffer of the HYS72T6400HFD-3S-B also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The Advanced Memory Buffer interface is responsible for handling channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the memory channel. Fully Buffered DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. The maximum memory capacity of the HYS72T6400HFD-3S-B is 288 DDR2 SDRAM devices per channel or 8 DIMMs.