HYS72T64000HP3B

• 240-Pin PC26400, PC25300 and PC24200 DDR2 SDRAM memory modules.
• One rank 64M *72, 128M *72, and two ranks 128M *72,256M *72 module organization, and 512M *8, 512M *4
chip organization
• Registered DIMM Parity bit for address and control bus
• 512 MB, 1 GB, and 2 GB module built with 512 Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply
• Programmable CAS Latencies (3, 4, 5, 6), Burst Length (4 & 8) and Burst Type
• Auto Refresh (CBR) and Self Refresh
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• All inputs and outputs SSTL_18 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT)
• Serial Presence Detect with E²PROM
• RDIMM Dimensions (nominal): 30 mm high, 133.35 mm wide
• Based on standard reference card layouts Raw Card "F","G", "H", "J" and "L"
• All speed grades faster than DDR2400 comply with DDR2400 timing specifications.
• RoHS compliant products1)

1) When V_DD and V_DDQ and V_DDL are less than 500 mV; V_REF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
  Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The HYS72T64000HP3B module family are Registered DIMM (with parity) modules with 30 mm height based on DDR2 technology. DIMMs are available as ECC modules in 64M * 72 (512 MB), 128M * 72 (1 GB), 256M x72 (2GB) organization and density,intended for mounting into 240-Pin connector sockets.

The memory array of the HYS72T64000HP3B is designed with 512-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors of the HYS72T64000HP3B are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.