HYS72T64000HP3.7A

1) When V_DD and V_DDQ and V_DDL are less than 500 mV; V_REF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
  Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The HYS72T64000HP3.7A module family are Registered DIMM (with parity) modules with 30 mm height based on DDR2 technology.

DIMMs of the HYS72T64000HP3.7A are available as ECC modules in 64M * 72 (512 MB),128M * 72 (1 GB), 256M x72 (2GB) organization and density,intended for mounting into 240-Pin connector sockets.

The memory array of the HYS72T64000HP3.7A is designed with 512-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature of the HYS72T64000HP3.7A serial presence detect based on a serial E²PROM device using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.