Features: • 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for 1U PC, Workstation and Server main memory applications• One rank 32 M * 72 and 64M * 72 and two ranks 64 M *72 and 128 M *72 organization• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with ...
HYS72D64300GBR5C: Features: • 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for 1U PC, Workstation and Server main memory applications• One rank 32 M * 72 and 64M * 72 and two ranks 64 M *72 a...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: • 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main...
Parameter |
Symbol |
Values
|
Unit |
Note/ Test Condition | ||
min. |
typ. |
max. | ||||
Voltage on I/O pins relative to VSS |
VIN, VOUT |
0.5 |
- |
VDDQ +0.5 |
V |
- |
Voltage on inputs relative to VSS |
VIN |
1 |
- |
+3.6 |
V |
- |
Voltage on VDD supply relative to VSS |
VDD |
1 |
- |
+3.6 |
V |
- |
Voltage on VDDQ supply relative to VSS |
VDDQ |
1 |
- |
+3.6 |
V |
- |
Operating temperature (ambient) |
TA |
0 |
- |
+70 |
°C |
- |
Storage temperature (plastic) |
TSTG |
-55 |
- |
+150 |
°C |
- |
Power dissipation (per SDRAM component) |
PD |
- |
1 |
- |
W |
- |
Short circuit output current |
IOUT |
- |
50 |
- |
mA |
- |
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
The HYS72D64300GBR5C are low profile versions of the standard Registered DIMM modules suitable for 1U Server Applications. The Low Profile DIMM versions are available as 32 M *72 (256 MB), 64 M *72 (512 MB) and 128 M *72 (1 GB)
The memory array of the HYS72D64300GBR5C is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.