HYB 39S16400CT-10

The HYB 39S16400CT-10/800/160CT are dual bank Synchronous DRAM's based on SIEMENS 0.25 mm process and organized as 2 banks ´ 2 MBit ´ 4, 2 banks ´ 1 MBit ´ 8 and 2 banks ´ 512 kbit ´ 16 respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS' advanced 16 MBit DRAM process technology.

The device HYB 39S16400CT-10 is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device HYB 39S16400CT-10. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3V ± 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.