Features: 16 Mbits * 16 organisationFully synchronous to positive clock edgeFour internal banks for concurrent operationData mask (DM) for byte control with write and read dataProgrammable CAS latency: 2 or 3Programmable burst length: 1, 2, 4, 8, or full pageProgrammable wrap sequence: sequential ...
HYB25L256160AC: Features: 16 Mbits * 16 organisationFully synchronous to positive clock edgeFour internal banks for concurrent operationData mask (DM) for byte control with write and read dataProgrammable CAS laten...
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Features: • Double data rate architecture: two data transfers per clock cycle• Bidirec...
Features: • Double data rate architecture: two data transfers per clock cycle• Bidirec...
The 256-Mbit Mobile-RAM HYB25L256160AC is a new generation of low power, four bank synchronous DRAM organized as 4 banks x 4 Mbit x 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The device HYB25L256160AC adds new features to the industry standards set for synchronous DRAM products. Parts of the memory array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. In addition a "Deep Power Down Mode" is available. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.
The Mobile-RAM HYB25L256160AC is housed in a FBGA "chip-size" package. The Mobile-RAM is available in the commerical (0 to 70 ) temperature range.