Features: `Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• RAS-lockout supported tRAP = tRCD
• 7.8s Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
• VDDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333);
VDDQ = 2.6 V ± 0.1 V (DDR400)
• VDD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333);
VDD = 2.6 V ± 0.1 V (DDR400)
• Standard Temperature Range (0 - +70 ) or Industrial Temperature Range (40 - +85 )
• P-TFBGA-60-12 package with 3 depopulated rows (8 * 12 mm2)
• P-TSOPII-66 package
• RoHS1) compliant product types available (green product)Specifications
|
Parameter |
Symbol |
Values |
Unit |
Note/ Test Condition |
|
Min. |
Typ. |
Max. |
|
Voltage on I/O pins relative to VSS |
VIN, VOUT |
0.5 |
- |
VDDQ + 0.5 |
V |
|
|
Voltage on inputs relative to VSS |
VIN |
1 |
- |
+3.6 |
V |
|
|
Voltage on VDD supply relative to VSS |
VDD |
1 |
- |
+3.6 |
V |
|
|
Voltage on VDDQ supply relative to VSS |
VDDQ |
1 |
- |
+3.6 |
V |
|
|
Operating temperature (ambient) |
TA |
0 |
- |
+70 |
|
HYB |
|
40 |
- |
+85 |
|
HYI |
|
25 |
- |
+85 |
|
HYE |
|
Storage temperature (plastic) |
TSTG |
55 |
- |
+150 |
|
|
|
Power dissipation (per SDRAM component) |
PD |
- |
1 |
- |
W |
|
|
Short circuit output current |
IOUT |
- |
50 |
- |
mA |
|
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
DescriptionThe 256 Mbit Double-Data-Rate SDRAM HYB25D256800CE5A is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 256 Mbit Double-Data-Rate SDRAM HYB25D256800CE5A uses a doubledata- rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256 Mbit Double-Data-Rate SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM HYB25D256800CE5A during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes.
The 256 Mbit Double-Data-Rate SDRAM HYB25D256800CE5A operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM HYB25D256800CE5A provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
HYB25D256800CE5A Data Sheet
