HY5DU56422BT-D4/D43

      This is the description about the HY5DU56422BT-D4/D43 and the HY5DU56822BT-D4/D43. The Hynix HY5DU56422BT, HY5DU56822BT are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
      Here are the HY5DU56422BT-D4/D43 features: VDD/VDDQ = 2.5 ~ 2.7V; All inputs and outputs are compatible with SSTL_2 interface; Fully differential clock inputs (CK, /CK) operation; Double data rate interface; Source synchronous - data transaction aligned to bidirectional data strobe (DQS; x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O; On chip DLL align DQ and DQS transition with CK transition.
      The HY5DU56422BT-D4/D43 absolute Maximum Ratings (TA = 25) are these. Ambient Temperature is from 0 to 70oC. Storage Temperature is from -55 to 125oC. Voltage on Any Pin relative to VSS is from -0.5 to 3.6V. Voltage on VDD relative to VSS is from -0.5 to 3.6V. Voltage on VDDQ relative to VSS is from -0.5 to 3.6V. Output Short Circuit Current is 50mA. Power Dissipation is 1W. Soldering temperature*Time is 260 *10                     oC*sec.
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