HY5DU561622ETP-D43-C

The HY5DU561622ETP-D43-C is a kind of 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, which is ideally suited for the point-to-point applications that requires high bandwidth.It provides fully synchronous operations referenced to both rising and falling edges of the clock.

Features of the HY5DU561622ETP-D43-C are:(1) 2.5V +/-5% VDD and VDDQ power supply supports 250/200 Mhz;(2) 2.6V +/- 0.1V VDD/VDDQ power supply supports 300/ 275Mhz;(3) 2.8V +/- 0.1V VDD/ VDDQ power supply supports 350Mhz;(4) all inputs and outputs are compatible with SSTL_2 interface;(5) JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch;(6) fully differential clock inputs (CK, /CK) operation;(7) double data rate interface;(8) source synchronous - data transaction aligned to bidirectional data strobe (DQS);(9) x16 device has 2 bytewide data strobes (LDQS,UDQS) per each x8 I/O.

The absolute maximum ratings of the HY5DU561622ETP-D43-C can be summarized as:(1): ambient temperature(TA) is 0 to 70;(2): storage temperature(TSTG) is -55 to 125;(3): voltage on any pin relative to VSS(VIN, VOUT) is  -0.5 V to 3.6 V;(4): voltage on VDD relative to VSS(VDD) is -0.5 V to 3.6 V; (5): voltage on VDDQ relative to VSS(VDDQ) is -0.5 V to 3.6 V;(6): output short circuit current(IOS) is 50 mA;(7): power dissipation(PD) is 1 W.