HY5DU28822

• 2.5V VDD and VDDQ power suppliy
• All inputs and outputs are compatible with SSTL_2 interface
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Fully differential clock operations(CLK & CLK) with 100MHz/125MHz/133MHz
• All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock
• Data(DQ) and Write masks(DM) latched on both rising and falling edges of the Data Stobe
• Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
• Delay Locked Loop(DLL) installed with DLL reset mode
• Write mask byte controlled by DM
• Programmable CAS Latency 2 and 2.5 supported
• Write Operations with 1 Clock Write Latency
• /QFC & Half Strength Driver controlled by EMRS
• Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• 4096 refresh cycles / 64ms

The Hyundai HY5DU28822 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU28822 is organized as 4 banks of 4,194,304x8.

HY5DU28822 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data strobes(DQS) and Write data masks(DM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit p refetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

HY5DU28822 Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5), the number of consecutive read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled
through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM.