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HY5DU121622A

Features: • VDD, VDDQ = 2.5V +/- 0.2V• All inputs and outputs are compatible with SSTL_2 interface• Fully differential clock inputs (CK, /CK) operation • Double data rate interface• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)•...

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SeekIC No. : 004368276 Detail

HY5DU121622A: Features: • VDD, VDDQ = 2.5V +/- 0.2V• All inputs and outputs are compatible with SSTL_2 interface• Fully differential clock inputs (CK, /CK) operation • Double data rate int...

HY5DU121622A Data Sheet

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Part Number:
HY5DU121622A
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• VDD, VDDQ = 2.5V +/- 0.2V
• All inputs and outputs are compatible with SSTL_2 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)Data inputs on DQS centers when write (centered DQ)
• On chip DLL align DQ and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable /CAS latency 2 / 2.5/ 3 supported
• Programmable burst length 2 / 4 / 8 with both sequential and interleave mode
• Internal four bank operations with single pulsed /RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Full and Half strength driver option controlled by EMRS


Pinout

Connection Diagram


Specifications

Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
Storage Temperature
TSTG
-55 ~ 125
Voltage on Any Pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD relative to VSS
VDD
-0.5 ~ 3.6
V
Voltage on VDDQ relative to VSS
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature Þ Time
TSOLDER
260 Þ 10
Þ sec
Note : Operation at above absolute maximum rating can adversely affect device reliability


Description

The HY5DU12422A(L)T, HY5DU12822A(L)T and HY5DU121622A(L)T are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.

This Hynix 512Mb DDR SDRAMs HY5DU121622A offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.




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