HY39S256

The HY39S256 are four bank Synchronous DRAMs organized as 4 banks x 16 MBit x4, 4 banks x 8 MBit x8 and 4 banks x 4 Mbit x16 respectively. These synchronous devices achieve high speed data  ransfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with Qimonda's advanced 0.11-m 256-MBit DRAM process technology. The device HY39S256 is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs HY39S256. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices HY39S256 operate with a single 3.3 V ± 0.3 V power supply.

All 256-Mbit components are available in P(G)TSOPII54 and PGTFBGA54 packages