HY39S128800FL

The HY39S128800FL are four bank Synchronous DRAM's organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with Qimonda's advanced 0.11 m 128-MBit DRAM process technology.

The device HY39S128800FL is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device HY39S128800FL.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices HY39S128800FL operate with a single 3.3 V ± 0.3 V power supply.

All 128-Mbit components are available in P(G)TSOPII54 packages.