Features: ` 5 Volt Read, Program, and Erase
Minimizes system-level power requirements
` High Performance
Access times as fast as 55 ns
` Low Power Consumption
20 mA typical active read current in byte mode, 28 mA typical in word mode
35 mA typical program/erase current
5 A maximum CMOS standby current
` Compatible with JEDEC Standards
Package, pinout and command-set compatible with the single-supply Flash device standard
Provides superior inadvertent write protection
` Sector Erase Architecture
Boot sector architecture with top and bottom boot block options available
One 16 Kbyte, two 8 Kbyte, one 32 Kbyte and fifteen 64 Kbyte sectors in byte mode
One 8 Kword, two 4 Kword, one 16 Kword and fifteen 32 Kword sectors in word mode
A command can erase any combination of sectors
Supports full chip erase
` Erase Suspend/Resume
Temporarily suspends a sector erase peration to allow data to be read from, or programmed into, any sector not being erased
` Sector Protection
Any combination of sectors may be locked to prevent program or erase operations within those sectors
` Temporary Sector Unprotect
Allows changes in locked sectors (requires high voltage on RESET# pin)
` Internal Erase Algorithm
Automatically erases a sector, any combination of sectors, or the entire chip
` Internal Programming Algorithm
Automatically programs and verifies data at a specified address
` Fast Program and Erase Times
Byte programming time: 7 s typical
Sector erase time: 1.0 sec typical
Chip erase time: 19 sec typical
` Data# Polling and Toggle Status Bits
Provide software confirmation of completion of program or erase operations
` Ready/Busy# Output (RY/BY#)
Provides hardware confirmation of completion of program and erase operations
` Minimum 100,000 Program/Erase Cycles
` Space Efficient Packaging
Available in industry-standard 44-pin PSOP and 48-pin TSOP and reverse TSOP packagesPinout
Specifications
|
Symbol |
Parameter |
Value |
Unit |
|
TSTG |
Storage Temperature |
-65 to +125 |
|
|
TBIAS |
Ambient Temperature with Power Applied |
-55 to +125 |
|
|
VIN2 |
Voltage on Pin with Respect to V SS :
VCC1
A[9], OE#, RESET# 2
All Other Pins 1 |
-2.0 to +7.0
-2.0 to +12.5
-2.0 to +7.0 |
V
V
V |
|
IOS |
Output Short Circuit Current 3 |
200 |
mA |
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10.
2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET# may undershoot VSS to 2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second.
4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional peration of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
DescriptionThe HY29F800 is an 8 Megabit, 5 volt only CMOS Flash memory organized as 1,048,576 (1M) bytes or 524,288 (512K) words. The device is offered in industry-standard 44-pin PSOP and 48-pin TSOP packages.
The HY29F800 can be programmed and erased in-system with a single 5-volt VCC supply. Internally generated and regulated voltages are provided for rogram and erase operations, so that the device does not require a high voltage power supply to perform those functions. The device can also be rogrammed in standard EPROM programmers. Access times as fast as 70 ns over the full operating voltage range of 5.0 volts ± 10% are offered for timing compatibility with the zero wait state requirements of high speed micropro-cessors. A 55 ns version operating over 5.0 volts ± 5% is also available. To eliminate bus contention, the HY29F800 has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The device is compatible with the JEDEC single power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte at a time by executing the four-cycle Program Command. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.
The HY29F800's sector erase architecture allows any number of array sectors to be erased and reprogrammed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase Command. This initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase cycles, the device automatically times the erase pulse widths and verifies proper cell margin. To protect data in the device from accidental or unauthorized attempts to program or erase the device while it is in the system (e.g., by a virus), the device has a Sector Protect function which hardware write protects selected sectors. The sector protect and unprotect features can be enabled in a PROM programmer. Temporary Sector Unprotect, which requires a high voltage, allows in-system erasure and code changes in previously protected sectors.
Erase Suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device HY29F800 is fully erased when shipped from the factory.
Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (toggle) status bits. Reading data from the device HY29F800 is similar to reading from SRAM or EPROM devices. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions.
The host can place the device HY29F800 into the standby mode. Power consumption is greatly reduced in this mode.
HY29F800 Data Sheet
