HY29DL162

Single Power Supply Operation
− Read, program, and erase operations from 2.7 to 3.6 V
− Ideal for battery-powered applications

Simultaneous Read/Write Operations
− Host system can program or erase in one bank while simultaneously reading from any sector in the other bank with zero latency between read and write operations

High Performance
− 70 and 80 ns access time versions with 30pF load
− 90 and 120 ns access time versions with 100pF load

Ultra Low Power Consumption (Typical Values)
− Automatic sleep mode current: 200 nA
− Standby mode current: 200 nA
− Read current: 10 mA (at 5 MHz)
− Program/erase current: 15 mA

Boot-Block Sector Architecture with 39 Sectors in Two Banks for Fast In-System Code Changes

Secured Sector: An Extra 64 Kbyte Sector that Can Be:
− Factory locked and identifiable: 16 bytes available for a secure, random factoryprogrammed Electronic Serial Number
− Customer lockable: Can be read, programmed, or erased just like other sectors

Flexible Sector Architecture
− Sector Protection allows locking of a sector or sectors to prevent program or erase operations within that sector
− Temporary Sector Unprotect allows changes in locked sectors (requires high voltage on RESET# pin)

Automatic Erase Algorithm Erases Any Combination of Sectors or the Entire Chip

Automatic Program Algorithm Writes and Verifies Data at Specified Addresses

Compliant with Common Flash Memory Interface (CFI) Specification

Minimum 100,000 Write Cycles per Sector (1,000,000 cycles Typical)

Compatible with JEDEC Standards
− Pinout and software compatible with single-power supply Flash devices
− Superior inadvertent write protection

Data# Polling and Toggle Bits
− Provide software confirmation of completion of program or erase operations

Ready/Busy# Pin
− Provides hardware confirmation of completion of program or erase operations

Erase Suspend
− Suspends an erase operation to allow programming data to or reading data from a sector in the same bank
− Erase Resume can then be invoked to complete the suspended erasure

Hardware Reset Pin (RESET#) Resets the Device to Reading Array Data

WP#/ACC Input Pin
− Write protect (WP#) function allows hardware protection of two outermost boot sectors, regardless of sector protect status
− Acceleration (ACC) function provides accelerated program times

Fast Program and Erase Times
− Sector erase time: 0.5 sec typical
− Byte/Word program time utilizing Acceleration function: 10 s typical

Space Efficient Packaging
− 48-pin TSOP and 48-ball FBGA packages

Notes:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

2. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to V_CC +2.0 V for periods up to 20 ns. See Figure 10.

3. Minimum DC input voltage on pins WP#/ACC, A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE# and RESET# may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pins A[9], OE#, and RESET#] is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. Maximum DC input voltage on pin WP#/ACC is +9.5 V which may overshoot to 12.0 V for periods up to 20 ns.

4. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second.

The HY29DL162/HY29DL163 (HY29DL16x) is a 16 Mbit, 3 volt-only CMOS Flash memory organi zed as 2,097,152 (2M) bytes or 1,048,576 (1M) words. The device is available in 48-pin TSOP and 48-ball FBGA packages. Word-wide data (x16) appears on DQ[15:0] and byte-wide (x8) data appears on DQ[7:0].

The HY29DL162 Flash memory array is organized into 39 sectors in two banks. Bank 1 contains eight 8 Kbyte boot/parameter sectors and 3 or 7 larger sectors of 64 Kbytes each, depending on the version of the device. Bank 2 contains the rest of the memory array, organized as 28 or 24 sectors of 64 Kbytes:

Bank 1                                         Bank 2
HY29DL162 8 x 8KB/4KW
3 x 64KB/32KW                       28 x 64KB/32KW
HY29DL163 8 x 8KB/4KW
7 x 64KB/32KW                      24 x 64KB/32KW

The device HY29DL162 features simultaneous read/write operation which allows the host system to invoke a program or erase operation in one bank and immediately and simultaneously read data from the other bank, except if that bank has any sectors marked for erasure, with zero latency. This releases the system from waiting for the completion of program or erase operations, thus improving overall system performance.

The HY29DL162 can be programmed and erased in-system with a single 2.7 - 3.6 volt V_CC supply.

Internally generated and regulated voltages are provided for program and erase operations, so that the device HY29DL162 does not require a higher voltage VPP power supply to perform those functions. The device can also be programmed in standard EPROM programmers. Access times as low as 70 ns are offered for timing compatibility with the zero wait state requirements of high speed microprocessors.

To eliminate bus contention, the HY29DL162 has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device HY29DL162 is compatible with the JEDEC singlepower- supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits.

Device programming is performed a byte/word at a time by executing the four-cycle Program Command write sequence. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Faster programming times can be achieved by placing the HY29DL162 in the Unlock Bypass mode, which requires only two write cycles to program data instead of four.

The HY29DL162's sector erase architecture allows any number of array sectors, in one or both banks, to be erased and reprogrammed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase Command sequence.

This initiates an internal algorithm that automatically preprograms the sector before executing the erase operation. As during programming cycles, the device HY29DL162 automatically times the erase pulse widths and verifies proper cell margin.

Hardware Sector Group Protection optionally disables both program and erase operations in any combination of the sector groups, while Temporary Sector Group Unprotect, which requires a high voltage on one pin, allows in-system erasure and code changes in previously protected sector groups. Erase Suspend enables the user of HY29DL162 to put erase on hold in a bank for any period of time to read data from or program data to any sector in that bank that is not selected for erasure.

True background erase can thus be achieved. Because the HY29DL162 features simultaneous read/write capability, there is no need to suspend to read from a sector located within a bank that does not contain sectors marked for erasure. The device is fully erased when shipped from the factory.

Addresses and data needed for the programming and erase operations are internally latched during write cycles. The host system of HY29DL162 can detect completion of a program or erase operation by observing the RY/BY# pin or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. Hardware data protection measures include a low V_CC detector that automatically inhibits write operations
during power transitions.

After a program or erase cycle has been completed, or after assertion of the RESET# pin (which terminates any operation in progress), the device HY29DL162 is ready to read data or to accept another com-mand. Reading data out of the device is similar to
reading from other Flash or EPROM devices.

The HY29DL162 Secured Sector is an extra 64 Kbyte sector capable of being permanently locked at the factory or by customers. The Secured Indicator Bit (accessed via the Electronic ID mode) is permanently set to a 1 if the part is factory locked, and permanently set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The Secured Sector may store a secure, random 16-byte ESN (Electronic Serial Number), customer code programmed at the factory, or both. Customer Lockable parts may utilize the Secured Sector as bonus space, reading and writing like any other Flash sector, or may permanently lock their own code there. The WP#/ACC pin provides access to two functions.

The HY29DL162 Write Protect function provides a hardware method of protecting certain boot sectors without using a high voltage. The Accelerate function speeds up programming operations, and is intended primarily to allow faster manufacturing throughput.

Two power-saving features are embodied in the HY29DL16x. When addresses have been stable for a specified amount of time, the device HY29DL162 enters the automatic sleep mode. The host can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.