HY29F400A

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may undershoot V_SS to -2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is V_CC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to V_CC +2.0 V for periods up to 20 ns. See Figure 10.
2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET# may undershoot V_SS to 2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5 V which may overshoot to 13.5 V for periods up to 20 ns.
3. No more than one output at a time may be shorted to V_SS. Duration of the short circuit should be less than one second.
4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

The HY29F400A is a 4 Megabit, 5 volt only CMOS Flash memory organized as 524,288 (512K) bytes or 262,144 (256K) words. The device is offered in industry-standard 44-pin PSOP and 48-pin TSOP packages.

The HY29F400A can be programmed and erased in-system with a single 5-volt V_CC supply. Internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a high voltage power supply to perform those functions. The device can also be programmed in standard EPROM programmers. Access times as fast as 55 ns over the full operating voltage range of 5.0 volts ± 10% are offered for timing compatibility with the zero wait state requirements of high speed microprocessors. A 55 ns version operating over 5.0 volts ± 5% is also available. To eliminate bus contention, the HY29F400A has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device HY29F400A is compatible with the JEDEC single power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte or word at a time by executing the four-cycle Program command. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

The HY29F400A's sector erase architecture allows any number of array sectors to be erased and reprogrammed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase command. This initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase cycles, the device automatically times the erase pulse widths and verifies proper cell margin.

To protect data in the device HY29F400A from accidental or unauthorized attempts to program or erase the device while it is in the system (e.g., by a virus), the device has a Sector Protect function which hardware write protects selected sectors. The sector protect and unprotect features can be enabled in a PROM programmer. Temporary Sector Unprotect, which requires a high voltage, allows in-system erasure and code changes in previously protected sectors.

Erase Suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device HY29F400A is fully erased when shipped from the factory.

Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. Reading data from the device is similar to reading from SRAM or EPROM devices. Hardware data protection measures include a low V_CC detector that automatically inhibits write operations during power transitions.

The host can place the device HY29F400A into the standby mode. Power consumption is greatly reduced in this mode.