Features: • Up to 65 MSPS Front-End Processing Rates (CLKIN) and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous• Processing Capable of >100dB SFDR• Up to 255-Tap Programmable FIR• Overall Decimation Factor Ranging...
HSP50214A: Features: • Up to 65 MSPS Front-End Processing Rates (CLKIN) and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous• Processing Capa...
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Features: • Single HSP50016-EV May be Used to Evaluate the HSP50016• May be Daisy Chai...
The HSP50214A Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter (PDC) performs down conversion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion.
The 14-bit sampled IF input is down converted to baseband by digital mixers and a quadrature NCO, as shown in the Block Diagram. A decimating (4 to 32) fifth order Cascaded Integrator-Comb (CIC) filter can be applied to the data before it is processed by up to 5 decimate-by-2 halfband filters. The halfband filters are followed by a 255-tap programmable FIR filter. The output data from the programmable FIR filter is scaled by a digital AGC before being re-sampled in a polyphase FIR filter. The HSP50214A output section can provide seven types of data: Cartesian (I, Q), polar (R, q), filtered frequency (dq/dt), Timing Error (TE), and AGC level in either parallel or serial format.