HSP50214

Features: • Up to 52 MSPS Front-End Processing Rates (CLKIN) and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous• Processing Capable of >100dB SFDR8-• Up to 255-Tap Programmable FIR• Overall Decimation Factor Ranging from 4 to 16384• Output S...

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SeekIC No. : 004366459 Detail

HSP50214: Features: • Up to 52 MSPS Front-End Processing Rates (CLKIN) and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous• Processing Capable of >100dB SFDR8-• Up ...

floor Price/Ceiling Price

Part Number:
HSP50214
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Up to 52 MSPS Front-End Processing Rates (CLKIN) and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous
• Processing Capable of >100dB SFDR8-
• Up to 255-Tap Programmable FIR
• Overall Decimation Factor Ranging from 4 to 16384
• Output Samples Rates to ≅8.2 MSP8-S with Output Bandwidths to ≅625kHz Lowpass
• 32-Bit Programmable NCO for Channel Selection and Carrier Tracking
• Digital Re-Sampling Filter for Symbol Tracking Loops and Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Sle8- Rate to Optimize Output Signal Resolution; Fixed or Auto Gain Adjust
• Serial, Parallel, and FIFO 16-Bit Output Modes
• Cartesian to Polar Converter and Frequency Discriminator for AFC Loops and Demodulation of AM, FM, FSK, and DPSK
• Input Level Detector for External I.F. AGC Support



Application

• Single Channel Digital Software Radio Receivers
• Base Station Rx's: AMPS, NA TDMA, GSM, and CDMA
• Compatible with HSP50210 Digital Costas Loop for PSK Reception
• Evaluation Platform Available



Pinout

  Connection Diagram


Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . .  GND-0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2



Description

The HSP50214 Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter (PDC) performs down conversion, decimation, narrowband low pass filtering, gain scaling, re-sampling, and Cartesian to Polar coordinate conversion.

The 14-bit sampled IF input is down converted to baseband by digital mixers and a quadrature NCO, as shown in the Block Diagram. A decimating (4 to 32) fifth order Cascaded Integrator-Comb (CIC) filter can be applied to the data before it is processed by up to 5 decimate-by-2 halfband filters. The halfband filters are followed by a 255-tap programmable FIR filter. The output data from the programmable FIR filter is scaled by a digital AGC before being re-sampled in a polyphase FIR filter. The HSP50214 output section can provide seven types of data: Cartesian (I, Q), polar (R, ), filtered frequency (d/dt), timing error (TE), and AGC level in either parallel or serial format.




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