HSP48410

Features: • 10-Bit Pixel Data• 4k x 4k Frame Sizes• Asynchronous Flash Clear Pin• Single Cycle Memory Clear• Fully Asynchronous 16 or 24-Bit Host Interface• Generates and Stores Cumulative Distribution Function• Look Up Table Mode• 1024 x 24-Bit Dela...

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HSP48410 Picture
SeekIC No. : 004366445 Detail

HSP48410: Features: • 10-Bit Pixel Data• 4k x 4k Frame Sizes• Asynchronous Flash Clear Pin• Single Cycle Memory Clear• Fully Asynchronous 16 or 24-Bit Host Interface• Gener...

floor Price/Ceiling Price

Part Number:
HSP48410
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• 10-Bit Pixel Data
• 4k x 4k Frame Sizes
• Asynchronous Flash Clear Pin
• Single Cycle Memory Clear
• Fully Asynchronous 16 or 24-Bit Host Interface
• Generates and Stores Cumulative Distribution Function
• Look Up Table Mode
• 1024 x 24-Bit Delay Memory
• 24-Bit Three State I/O Bus
• DC to 40MHz Clock Rate



Application

• Histogramming
• Histogram Equalization
• Image and Signal Analysis
• Image Enhancement
• RGB Video Delay Line



Pinout

  Connection Diagram


Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  +8.0V
Input, Output Voltage . . . . . . . . . . . . . . . . . .GND-0.5V to VCC+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1



Description

The Intersil HSP48410 is an 84 lead Histogrammer IC intended for use in image and signal analysis. The on-board memory is configured as 1024 x 24 array. This translates to a pixel resolution of 10 bits and an image size of 4k x 4k with no possibility of overflow.

In addition to Histogramming, the HSP48410 can generate and store the Cumulative Distribution Function for use in Histogram Equalization applications. Other capabilities of the HSP48410 include: Bin Accumulation, Look Up Table, 24-bit Delay Memory, and Delay and Subtract mode.

A Flash Clear pin is available in all modes of operation and performs a single cycle reset on all locations of the internal memory array and all internal data paths.

The HSP48410 includes a fully asynchronous interface which provides a means for communications with a host, such as a microprocessor. The interface includes dedicated Read/Write pins and an address port which are asynchronous to the system clock. This allows random access of the Histogram Memory Array for analysis or conditioning of the stored data.




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