HSD8M64D4B

Features:

• Part Identification
   HSD8M64D4B-10 : 100MHz ( CL=2)
   HSD8M64D4B-10L : 100MHz ( CL=3)
   HSD8M64D4B- 13 : 133MHz ( CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
   - Latency (Access from column address)
   - Burst length (1, 2, 4, 8 & Full page)
   - Data scramble (Sequential & Interleave)
• JEDEC standard
• All inputs are sampled at the positive going edge of the system clock
• The used device is2Mx16Bitx4Banks SDRAM


Specifications

PARAMETER	SYMBOL	RATING
Voltage on Any Pin Relative to Vss	VIN ,OUT	-1V to 4.6V
Voltage on Vcc Supply Relative to Vss	Vcc	-1V to 4.6V
Power Dissipation	PD	4W
Storage Temperature	TSTG	-55to 150
Short Circuit Output Current	IOS	50mA

Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.


Description

The HSD8M64D4B is a 8M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 2M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M64D4B is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.