HM6216255HC

Features: · Single 5.0 Vsupply : 5.0 V ± 10 %· Access time: 10 ns (max)· Completely static memory - No clock or timing strobe required· Equal access and cycle times· Directly TTL compatible - All inputs and outputs· Operating current: 170 mA (max)· TTL standby current: 40 mA (max)· CMOS standby cu...

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HM6216255HC Picture
SeekIC No. : 004363486 Detail

HM6216255HC: Features: · Single 5.0 Vsupply : 5.0 V ± 10 %· Access time: 10 ns (max)· Completely static memory - No clock or timing strobe required· Equal access and cycle times· Directly TTL compatible - All in...

floor Price/Ceiling Price

Part Number:
HM6216255HC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/4

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Product Details

Description



Features:

·  Single 5.0 Vsupply : 5.0 V ± 10 %
·  Access time: 10 ns (max)
·  Completely static memory
     - No clock or timing strobe required
·  Equal access and cycle times
·  Directly TTL compatible
    - All inputs and outputs
·  Operating current: 170 mA (max)
·  TTL standby current: 40 mA (max)
·  CMOS standby current: 5 mA (max)
                                        : 1.2 mA (max) (L-version)
·  Data retansion current: 0.8 mA (max) (L-version)
·  Data retantion voltage: 2 V (min) (L-version)
·  Center VCC and VSS type pinout



Pinout

  Connection Diagram


Specifications

Parameter Symbol Value Unit
Supply voltage relative to VSS VCC 0.5 to +7.0 V
Voltage on any pin relative to VSS VT 0.5*1 to VCC+0.5*2 V
Power dissipation PT 1.0 W
Operating temperature Topr 0 to +70
Storage temperature Tstg 55 to +125
Storage temperature under bias Tbias 10 to +85



Description

The HM6216255HC Series is a 4-Mbit high speed static RAM organized 256-k word ´ 16-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. HM6216255HC is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in 400- mil 44-pin plastic SOJ and 400-mil 44-pin plastic TSOPII.


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