HM5117405 Series

Features: SpecificationsDescription The HM5117405 Series has the following features including Single 5 V ( 10%);Access time: 50 ns/60 ns/70 ns (max);Power dissipationActive mode : 495 mW/440 mW/385 mW (max) (HM5116405 Series),: 550 mW/495 mW/440 mW (max) (HM5117405 Series),Standby mode : 11 mW (ma...

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SeekIC No. : 004363326 Detail

HM5117405 Series: Features: SpecificationsDescription The HM5117405 Series has the following features including Single 5 V ( 10%);Access time: 50 ns/60 ns/70 ns (max);Power dissipationActive mode : 495 mW/440 mW/385 ...

floor Price/Ceiling Price

Part Number:
HM5117405 Series
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/31

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Product Details

Description



Features:






Specifications






Description

      The HM5117405 Series has the following features including Single 5 V ( 10%);Access time: 50 ns/60 ns/70 ns (max);Power dissipationActive mode : 495 mW/440 mW/385 mW (max) (HM5116405 Series),: 550 mW/495 mW/440 mW (max) (HM5117405 Series),Standby mode : 11 mW (max): 0.83 mW (max) (L-version);EDO page mode capability;Long refresh period 4096 refresh cycles : 64 ms (HM5116405 Series),: 128 ms (L-version),2048 refresh cycles : 32 ms (HM5117405 Series): 128 ms (L-version);3 variations of refresh etc.
      The Hitachi  HM5117405 Series are CMOS dynamic RAMs organized 4,194,304-word 4-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5117405 Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have package variations of standard 26-pin plastic SOJ and standard 26-pin plastic TSOP II. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet.tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode cycle (EDO page mode mix cycle (1), (2)), minimum value of cycle (tCAS + tCP + 2 tT) becomes greater than the specified tHPC (min) value. The value of cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2).
      Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd.   At present there is not too much information about this model.If you are willing to find more  about HM5117405 Series, please pay attention to our web! We will promptly update the relevant information.






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