HIP7010

Features: • Fully Supports VPW (Variable Pulse Width) Messaging Practices of SAE J1850 Standard for Class B Data Communications Network Interface- 3-Wire, High-Speed, Synchronous, Serial Interface• Reduces Wiring Overhead• Directly Interfaces with 68HC05 and 68HC11 Style SPI Port...

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SeekIC No. : 004362776 Detail

HIP7010: Features: • Fully Supports VPW (Variable Pulse Width) Messaging Practices of SAE J1850 Standard for Class B Data Communications Network Interface- 3-Wire, High-Speed, Synchronous, Serial Inter...

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Part Number:
HIP7010
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Description



Features:

• Fully Supports VPW (Variable Pulse Width) Messaging
  Practices of SAE J1850 Standard for Class B Data
  Communications Network Interface
- 3-Wire, High-Speed, Synchronous, Serial Interface
• Reduces Wiring Overhead
• Directly Interfaces with 68HC05 and 68HC11 Style SPI Ports
• 1MHz, 8-Bit Transfers Between Host and HIP7010
  Minimize Host Service Requirements
• Automatically Transmits Properly Framed Messages
• Prepends SOF to First Byte and Appends CRC to Last Byte
• Fail-Safe Design Including, Slow Clock Detection
  Circuitry, Prevents J1850 Bus Lockup Due to System
  Errors or Loss of Input Clock
• Automatic Collision Detection
• End of Data (EOD), Break, Idle Bus, and Invalid Symbol
  (Noise/Illegal Symbols) Detection
• Supports In-Frame Responses with Generation of
  Normalization Bits (NB) for Type 1, Type 2, and Type 3 Messages
• Wait-For-Idle Mode Reduces Host Overhead During
  Non-Applicable Messages
• Status Register Flags Provide Information on Current
  Status of J1850 Bus
• Serial I/O Pins are Active Only During Transfers - Bus
  Available for Other Devices 95% of the Time
• TEST Pin Provides Built-in-Test Capabilities for
  In-System Diagnostics and Factory Testing
• High Speed (4X) Receive Mode for Production and
  Diagnostic Testing/Programming
• Operates with Wide Range of Input Clock Frequencies
• Power-Saving Power-Down Mode
• Full -40oC to +125oC Operating Range
• Single 3.0V to 6.0V Supply



Pinout

  Connection Diagram


Specifications

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7.0V
Input or Output Voltage
Pins with VDD Diode . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V
Pins without VDD Diode . . . . . . . . . . . . . . .  . . . . -0.3V to +10.0V
ESD Classification . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . Class 2
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2500 Gates



Description

The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a member of the Intersil family of low-cost multiplexed wiring ICs. The integrated functions of the HIP7010, J1850  provide the system designer with components key to building a "Class B" multiplexed communications network interface, which fully conforms to the VPW Multiplexed Wiring protocol specified in the SAE J1850 Standard. The HIP7010 is designed to interface with a wide variety of Host microcontrollers via a standard three wire, high-speed (1MHz), synchronous, serial interface. The HIP7010 automatically produces properly framed VPW messages, prepending the Start of Frame (SOF) symbol and calculating and appending the CRC check byte. All circuitry needed to decode incoming messages, to validate CRC bytes, and to detect Breaks, End of Data (EOD), Idle bus, and illegal symbols is included. In- Frame Responses (IFRs) are fully supported for Type 1, Type 2, and Type 3 messages, with the appropriate Normalization Bit automatically generated. The HCMOS design allows proper opeSration at various input frequencies from 2MHz to 12MHz. Connection to the J1850 Bus is via a Intersil HIP7020.




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