HDMP-2689

Features:

• 1.0625GBd and 2.125 GBd serial data rates
• TX and RX data rates independently selectable for each channel
• Fibre Channel (T11) compatible
• High speed differential serial I/O with matched 50Ω impedance
• Supports Fibre Channel Protocols FC0
• Dual mode SerDes operation with 10-bit parallel data interface and optional 8B/10B encode/decode
• Standard comma recognition for positive (0011111xxx) and negative (1100000xxx) disparity
• Source-centered, double data rate clocking of receive parallel data for 1.0625 GBd and 2.125 GBd serial rates
• Source synchronous double data rate clocking of transmit parallel data for 2.125 GBd serial rate
• Source synchronous single data rate clocking of transmit parallel data for 1.0625 GBd serial rate
• MII management interface for chip control and status
• 1.8V core power supply, 2.5V power supply for SSTL_2 I/O
• Independent channel power-down for power savings
• SSTL_2 compliant parallel I/O and byte clocks
• Low transmit jitter
• Pre-emphasis on serial outputs controllable via the management interface
• Loss of signal detection
• AC-coupled differential LVPECL reference clock input
• Input equalization
• Boundary scan IEEE 1149.1 compliant
• SerDes self-test capability using PRBS or user-defined patterns
• Local internal loop back of TX serial data to RX serial data by channel
• 289-pin PBGA
• Testjet compliant


Application

• Fibre Channel Arbitrated Loop
• Fast Serial Backplanes


Pinout




Specifications

SYMBOL	Parameter	Units	MIN	MAX
VDDQ	I/O supply voltage	V	-0.5	4.0
VDD	Supply voltage digital core	V	-0.5	3.0
VDDA	Analog supply voltage	V	-0.5	3.0
TSTG	Storage temperature (not biased)	°C	-55	125
TC	Case temperature, measured at top center of the package	°C	0	95
TJ	Junction temperature	°C	0	110
VINHS	High speed input voltage (single-ended)	V	-0.5	VDDA + 0.6
VINLVPECL	LVPECL input voltage (reference clock RFCP/N) (single-ended)	V	-0.5	VDDA + 0.6
VINSSTL	SSTL_2 input voltage	V	-0.5	VDDQ + 0.8
ESD	Electrostatic Discharge, Class 1	V	-1000	1000

Description

The HDMP-2689 SerDes chip transmits and receives high speed serial data over fiber optic or coaxial cable interfaces that conform to ANSI X3T11 Fibre Channel specification.HDMP-2689supports SerDes-only mode using a 10-bit data interface with optional 8B/10B encoding for fast backplane applications.

The HDMP-2689 runs at 2.125 GBd or 1.0625 GBd data rates and provides parallel-to-serial and serial-to-parallel conversion on four independent channels contained in one package. An onchip phase locked loop (PLL) synthesizes the high speed transmit clock from a low speed (106.25 MHz) reference. Each receiver's on-chip PLL synchronizes directly to the incoming data stream, providing clock and data recovery. Both the transmitter and receiver support differential I/O for fiber optic component interfaces, which minimizes crosstalk and maximizes signal integrity. HDMP-2689 Chip control and status are accessed via the Media Independent Interface (MII) defined in IEEE 802.3.