HDMP-2634

This data sheet describes the HDMP-2634 Serdes device for 2.5 GBd serial data rates.

The HDMP-2634 Serdes is a silicon bipolar integrated circuit in a metallized QFP package. It provides a low-cost physical layer solution for 2.5 GBd serial link interfaces including a complete Serialize/Deserialize (Serdes) function with transmit and receive sections in a single device. The HDMP-2634 is also capable of operating on 1.25 GBd serial links. Input pins TX_RATE and RX_RATE select the data rates on the transmit and receive sides, respectively.

As shown in Figure 1, the transmitter section accepts 10-bit wide parallel SSTL_2 data (TX[0:9]) and a 125 MHz SSTL_2 byte clock (TBC) and serializes them into a highspeed serial stream. The parallel data is expected to be "8B/10B" encoded data or equivalent. At the source, TX[0:9] and TBC switch synchronously with respect to a 125 MHz clock internal to the sender. New data are emitted on both edges of TBC; this is called Double Data Rate (DDR). The HDMP-2634 finds a sampling window between the two edges of TBC to latch TX[0:9] data into the input register of the transmitter section when TX_RATE=1. If TX_RATE=0, the user must ensure no data transitions on the falling edge of TBC and this edge is used to latch in parallel data resulting in a 1.25 GBd serial stream.

The HDMP-2634 transmitter section's PLL locks to the 125 MHz TBC. This clock is then multiplied by 20 to generate the 2500 MHz serial clock for the high-speed serial outputs. The high-speed outputs are capable of interfacing directly to copper cables or PCB traces for electrical transmission or to a separate fiber optic module for optical transmission. The high-speed outputs include usercontrollable skin-loss equalization to improve performance when driving copper lines.

The HDMP-2634 receiver section accepts a serial electrical data stream at 1.25 or 2.5 GBd and recovers 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the