Features: • IEEE 802.3z Gigabit Ethernet compatible, Supports 1250 MBd Gigabit Ethernet
• Based on X3T11 "10-Bit Specification"
• Low Power Consumption
• Transmitter and Receiver Functions Incorporated Onto a Single IC
• 10 mm, 64-Pin Plastic Package
• 5 Volt Tolerant I/Os
• 10-Bit Wide Parallel TTL Compatible I/Os
• Single +3.3 V Power Supply
• Differential PECL Clock Inputs
• Dual Serial I/O With Receive Select
• 2kV ESD Protection on All PinsApplication• 1250 MBd Gigabit Ethernet Interface
• High Speed Proprietary Interface
• Backplane Serialization/Bus ExtenderPinout
Specifications
| SYMBOL |
Parameter |
Units |
MIN |
MAX |
UNIT |
| VCC |
Supply Voltage |
V |
-0.5 |
5.0 |
V |
| VIN,TTL |
TTL Input Voltage |
V |
-0.7 |
VCC+2.8 |
V |
| VIN,HS_IN |
HS_IN Input Voltage |
V |
2.0 |
VCC |
V |
| IO,TTL |
TTL Output Source Current |
mA |
|
13 |
°C |
| TSTG |
TTL Output Source Current |
°C |
-65 |
+150 |
°C |
| Tj |
Junction Temperature |
°C |
0 |
+150 |
mA |
DescriptionThe HDMP-1638 transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package. HDMP-1638provides a low-cost, low-power physical layer solution for 1250 MBd Gigabit Ethernet or proprietary link interfaces. HDMP-1638provides complete Serialize/ Deserialize ("SerDes") for copper transmission, incorporating both the Gigabit Ethernet transmit and receive functions into a single device. This chip is used to build a high speed interface (as shown in Figure 1) while minimizing board space, power and cost. It is compatible with the IEEE 802.3z specification.
The HDMP-1638 transmitter section accepts 10-bit wide parallel TTL data and serializes this data into two high speed serial data streams. The parallel data is expected to be "8B/10B" encoded data, or equivalent.
This parallel data of HDMP-1638 is latched into the input register of the transmitter section on the rising edge of the 125 MHz reference clock (used as the transmit byte clock). The transmitter section's PLL locks to this user supplied 125 MHz byte clock. This clock is then multiplied by 10, to generate the 1250 MHz serial signal clock used to generate the high speed outputs. The high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission. The receiver section allows for the selection of one of two serial electrical data streams at 1250 MBd and recovers the original 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the high speed serial clock and data.
The serial data of HDMP-1638 is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment. The recovered parallel data is presented to the user at TTL compatible outputs.
The HDMP-1638 receiver section also recovers two 62.5 MHz receiver byte clocks which are 180 degrees out of phase with each other. The parallel data is properly aligned with the rising edge of alternating clocks. For test purposes, the transceiver provides for on-chip local loopback functionality controlled through an external input pin. Additionally, the byte synchronization feature may be disabled. This may be useful in proprietary applications which use alternative methods to align the parallel data.
HDMP-1638 Data Sheet
