HDMP-1637A

The HDMP-1637A transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package.HDMP-1637Aprovides a low-cost, low-power physical layer solution for 1250 MBd Gigabit Ethernet or proprietary link interfaces. HDMP-1637A provides complete Serialize/ Deserialize (SerDes) for copper transmission, incorporating both the Gigabit Ethernet transmit and receive functions into a single device. This HDMP-1637A chip is used to build a high speed interface (as shown in Figure 1) while minimizing board space, power, and cost. It is compatible with the IEEE 802.3z specification.

The HDMP-1637A transmitter section accepts 10-bit wide parallel TTL data and serializes this data into a high speed serial data stream. The parallel data is expected to be "8B/10B" encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the 125 MHz reference clock (used as the transmit byte clock). The transmitter section's PLL locks to this user supplied 125 MHz byte clock.

This clock is then multiplied by 10, to generate the 1250 MHz serial signal clock used to generate the high speed output. The high speed outputs of HDMP-1637A are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission. The receiver section accepts a serial electrical data stream at 1250 MBd and recovers the original 10-bit wide parallel data.

The receiver PLL locks onto the incoming serial signal and recovers the high speed serial clock and data. The serial data of HDMP-1637A is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment. The recovered parallel data is presented to the user at TTL compatible outputs.

The HDMP-1637A receiver section also recovers two 62.5 MHz receiver byte clocks which are 180 degrees out of phase with each other. The parallel data is properly aligned with the rising edge of alternating clocks. For test purposes, the transceiver provides for on-chip local loopback functionality controlled through an external input pin. Additionally, the byte synchronization feature may be disabled. This may be useful in proprietary applications which use alternative methods to align the parallel data.