HDMP-1546

The HDMP-1536/46 transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package. HDMP-1536/46  provides a low-cost, low-power physical layer solution for 1062.5 MBd Fibre Channel or proprietary link interfaces. HDMP-1536/46  provides complete FC-0 functionality for copper transmission, incorporating both the Fibre Channel FC-0 transmit and receive functions into a single device.

This HDMP-1536/46  chip is used to build a highspeed interface (as shown in Figure 1) while minimizing board space, power, and cost. It is compatible with both the ANSI X3.230-1994/AM 1 - 1996 document and the "Fibre Channel 10-bit Interface" specification.

The HDMP-1536/46  transmitter section accepts 10-bit wide parallel TTL data and multiplexes this data into a highspeed serial data stream. The parallel data is expected to be 8B/10B encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the 106.25 MHz reference clock (used as the transmit byte clock). The transmitter section's PLL locks to this user supplied 106.25 MHz byte clock. This clock is then multiplied by 10, to generate the 1062.5 MHz serial signal clock used to generate the highspeed output.

The high-speed outputs of HDMP-1536/46  are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber-optic module for optical transmission. The receiver section accepts a serial electrical data stream at 1062.5 MBd and recovers the original 10-bit wide parallel data.

The receiver PLL locks onto the incoming serial signal and recovers the high-speed serial clock and data. The serial data of HDMP-1536/46   is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment.

The recovered parallel data of HDMP-1536/46  is presented to the user at TTL compatible outputs. The receiver section also recovers two 53.125 MHz receiver byte clocks that are 180 degrees out of phase with each other. The parallel data is properly aligned with the rising edge of alternating clocks.

The HDMP-1536/46  transceiver provides for onchip local loop-back functionality, controlled through an external input pin. Additionally, the byte synchronization feature may be disabled. This may be useful in proprietary applications which use alternative methods to align the parallel data.