HDMP-1526

Features:

• ANSI X3.230-1994 Fibre Channel Compatible (FC-0)
• Supports Full Speed (1062.5 MBd) Fibre Channel
• Conforms to "Fibre Channel 10-Bit Interface" Specification
• Transmitter and Receiver Functions Incorporated onto a Single IC
• 10-Bit Wide Parallel TTL Compatible I/Os
• Single +5.0 V Power Supply


Application

• 1062.5 MBd Fibre Channel Interface
• Mass Storage System I/O Channel
• Work Station/Server I/O Channel
• High Speed Proprietary Interface


Pinout




Specifications

Symbol	Parameter	Units	Min.	Max.
VCC	Supply Voltage	V	-0.5	6.0
VIN,TTL	TTL Input Voltage	V	-0.7	VCC + 0.7
VIN,HS_IN	HS_IN Input Voltage	V	2.0	VCC
IO,TTL	TTL Output Source Current	mA		13
Tstg	Storage Temperature	°C	-40	+130
Tj	Junction Operating Temperature	°C	0	+130
	Maximum Assembly Temperature (for 10 seconds maximum)	°C		+260

Description

The HDMP-1526 transceiver is a single silicon bipolar integrated circuit packaged in an EDQuad package. HDMP-1526 provides a low-cost, low-power physical layer solution for 1062.5 MBd Fibre Channel or proprietary link interfaces. HDMP-1526 provides complete FC-0 functionality for copper transmission, incorporating both the Fibre Channel FC-0 transmit and receive functions into a single device. This chip is used to build a highspeed interface (as shown in Figure 1) while minimizing board space, power and cost. It is compatible with both the ANSI X3.230-1994 document and the "Fibre Channel 10-bit Interface" specification. The transmitter section accepts 10-bit wide parallel TTL data and multiplexes this data into a highspeed serial data stream.

The parallel data of HDMP-1526 is expected to be 8B/10B encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the 106.25 MHz reference clock (used as the transmit byte clock).

The HDMP-1526 transmitter section's PLL locks to this user supplied 106.25 MHz byte clock. This clock is multiplied by 10, to generate the 1062.5 MHz serial signal clock used to generate the high-speed output.

The high-speed outputs of HDMP-1526 are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber-optic module for optical transmission. The receiver section accepts a serial electrical data stream at 1062.5 MBd and recovers the original 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the high-speed serial clock and data.

The serial data of HDMP-1526 is converted back into 10-bit parallel data, recognizing the 8B/10B comma character to establish byte alignment. The recovered parallel data is presented to the user at TTL compatible outputs. The receiver section also recovers two 53.125 MHz receiver byte clocks that are 180 degrees out of phase with each other.

The parallel data of HDMP-1526 is aligned with the rising edge of alternating clocks. The transceiver provides for onchip local loop-back functionality, controlled through an external input pin. Additionally, the byte synchronization feature may be disabled. This may be useful in proprietary applications that use alternative methods to align the parallel data.