HDMP-1032

Features:

• 3.3 V supply, low power dissipation 590 mW Tx, 660 mW Rx
• On-chip encode/decode using Conditional Inversion Master Transition (CIMT) protocol
• 1:N broadcast ready configurable receiver inputs allow multi-point data broadcast using a single transmitter
• Parallel Automatic Synchronization System (PASS) allows receiver to read recovered words with local reference clock
• Robust simplex mode
• Wide range serial rate 260-1400 MBaud (user selectable)
• 5 V tolerant TTL interface 16 or 17 Bits wide
• Low cost 64 pin plastic package 14x14 mm2 PQFP


Application

• Cellular base station
• ATM switch
• Backplane/bus extender
• Video, image acquisition
• Point to point data link
• Implement SCI-FI standard


Pinout




Specifications

SYMBOL	Parameter	Unit	MIN	MAX
VCC	Supply Voltage	V	-0.5	5.0
VIN,TTL	TTL Input Voltage	V	-7.0	5.5
VIN,TTL	H50 Input Voltage	V	2.0	VCC
IO,TTL	TTL Output Source Current	mA		13
Tstg	Storage Temperature	°C	-65	+150
TJ	Junction Temperature	°C	0	+150
Tmax	Maximum Assembly Temperature (10 seconds maximum)	°C		+260

Description

The HDMP-1032 transmitter and HDMP-1034 receiver are used together to build a high-speed data link for point-to-point communication. These HDMP-1032 silicon bipolar transmitter and receiver chips are housed in standard plastic 64 pin PQFP packages.

From the user's viewpoint, these HDMP-1032 can be thought of as a "virtual ribbon cable" interface for the transmission of data and control words. A parallel word loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel and is then reconstructed into its original parallel form.
The HDMP-1032 channel can be either a coaxial copper cable or optical link The chip set hides from the user the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding.

The CIMT encoding scheme used ensures the DC balance of the serial line. When data or control words are not being sent the transmitter sends idle words. The serial data rate of the Tx/Rx link is selectable in three ranges and extends from 208 to 1120 Mbit/s. This translates into an encoded serial rate of 260 to 1400 MBaud. The parallel data interface is 16 bit TTL. A flag bit is also present and can be used as an extra 17th bit under the user's control. This bit can be used as an even or odd word indicator for dual-word transmission. The encoding of the flag bit can be scrambled to reduce the probability of erroneous word alignment. A user control space is also provided. If TXCNTL is asserted on the Tx chip, the least significant 14 bits of the data will be sent and the RXCNTL line on the Rx chip will indicate the data is a Control Word. At the Rx, the PASS feature allows the recovered words to be clocked out with the local REFCLK. This feature is particularly useful when the Tx clock and REFCLK are synchronous.The PASS system in HDMP-1032  also supports synchronization of multiple channels.

The HDMP-1032  chipset is compatible with previous versions of the G-Link chipset (HDMP-10x2/10x4) provided the latter are used in 16 bit Simplex with Periodic Sync Pulse or External Reference Oscillator Mode (Simplex Method II or III).