HDMP-0552

Features:

• Supports 1.0625/2.125 GBd Fibre Channel operation
• Quad PBC/CDR in one package
• CDR location determined by choice of cable input/output
• Amplitude valid detection on FM_NODE[0] input
• Data valid detection on FM_NODE[0] input
Run length violation detection
Comma detection
Configurable for both singleframe and multi-frame detection
• Speed select pin for 1 or 2 GBd operation
• Single REFCLK for 1 or 2 GBd operation
• CDR selectable via external pin
• Enable/disable equalizers on all inputs
• Enable/disable selected highspeed output drivers
• High speed LVPECL I/O
• Buffered line logic (BLL) outputs (no external bias resistors required)
• 1.1 W typical power at VCC = 3.3 V
• Advanced 0.35 µ BiCMOS technology
• 64 Pin, 10 mm, low cost plastic QFP package


Application

• RAID, JBOD, BTS cabinets
• 1=> 1-4 serial buffer with or without CDR


Pinout




Specifications

Symbol	Parameter	Units	Minimum	Maximum
VCC	Supply Voltage	V	-0.7	4.0
VIN, LVTTL	LVTTL Input Voltage	V	-0.7	5.0
VIN,HS_IN	HS_IN Input Voltage	V	2.0	VCC
IO,LVTTL	LVTTL Output Current	mA		+13
Tstg	Storage Temperature	°C	-65	+150
Tj	Junction Temperature	°C	0	+125

Description

The HDMP-0552 is a Quad Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. See Figure 1 for block diagram. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system.

A PBC consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed." When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0552's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC (for example, an HDMP-263x) Rx± differential input pins. Data from the Disk Drive Transceiver IC Tx± differential output pins goes to HDMP-0552's FM_NODE[n]± differential input pins. Figure 2 and Figure 3 show connection diagrams for disk drive array applications.

When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional, and the loop bypasses the hard disk. Multiple HDMP-0552's may be cascaded or connected to other members of the HDMP-04xx family through the FM_LOOP and TO_LOOP pins to create loops for arrays of disk drives greater than 4. See Table 3 to identify which of the 5 cells (0:4) provides FM_LOOP, TO_LOOP pins (cell connected to cable).